(a) Field of the Invention
The present invention relates to a technique of manufacturing a wiring board for use in mounting of a chip component such as a semiconductor device, and more particularly to a multilayer wiring board having a multilayer structure adapted to achieve high density and a method of manufacturing the same.
(b) Description of the Related Art
To fabricate a wiring board of multilayer structure formed of a plurality of wiring boards stacked up with an insulating adhesive layer such as prepreg being provided therebetween, various approaches and technologies have been heretofore used as methods of interconnecting wiring patterns formed on the wiring boards. For example, FIG. 7A shows one of the methods. In this method, two wiring boards 1 and 2 each having wiring patterns formed on both sides are first stacked up with an insulating layer 3 (e.g., prepreg) sandwiched therebetween. Then, a through hole TH is formed in the stacked boards at a desired position by means of mechanical drilling or the like. Thereafter, electroplating is performed in the through hole TH (i.e., a conductor layer is formed), so that the wiring patterns on the wiring boards are interconnected through the conductor layer. Another method is to use B2IT (Buried Bump Interconnection Technology) for interconnecting the patterns between the boards. FIG. 7B shows an example of the method using B2IT. Conductive paste such as solder is first fed onto a wiring pattern of one board 5 by means of screen printing. The conductive paste is melted into a bump (namely, a solder bump 6) by means of reflow. Then, the solder bump 6 is press-bonded through a prepreg layer 7 to a wiring pattern of the other board 8. Still another method is to form gold (Au) bumps, copper (Cu) posts, or the like, on wiring patterns of wiring boards, thereby interconnecting the boards through a conductive material such as solder.
In any of the cases where these approaches and technologies are used for an interconnection between boards, misalignment, inaccuracy in fabrication, or the like, involved in stacking of the boards, must be taken into consideration. Accordingly, as shown in FIGS. 7A and 7B, connection pads 4 and 9 are formed at desired positions on the wiring patterns of the boards in such a manner as to have sizes larger than the diameters of the through hole TH and the bump 6 for use in the interconnection. The wiring patterns of the boards are thus electrically interconnected with their corresponding wiring patterns through the connection pads.
Japanese unexamined Patent Publication (JPP) (Kokai) 8-195561 describes one of the techniques related to the above prior art. In this technique, a multilayer printed wiring board includes a conductive bump formed of a synthetic resin in truncated cone form, fixedly bonded, at a first bottom face thereof on the small area side, to an outer pad, while being fixedly bonded, at a second bottom face thereof on the large area side, to copper foil of an inner conductor disposed inside, and formed of a laminate of synthetic resin sheet bases. Another related art is disclosed in JPP (Kokai) 8-125344. In this technique, a method of manufacturing a printed wiring board includes forming a desired conductive pattern on the surface of an insulating substrate; forming a conductive bump at a predetermined position on the surface of the conductive pattern; and then press-bonding copper foil to the surface having the conductive bump formed thereon, with an insulating adhesive resin layer being provided therebetween, in which the conductive bump is connected at the end through the insulating adhesive resin layer to the surface of the copper foil opposite to the bump.
As mentioned above, the conventional manufacturing technology for a multilayer wiring board adopts the through hole (and plating in the through hole), the solder bump, the Au bump, the Cu post, or the like, as means for interconnecting the boards (or the wiring patterns). However, any means requires a circular connection pad of appropriate size (e.g., the connection pads 4 and 9 shown in FIGS. 7A and 7B), allowing for the misalignment, the inaccuracy in fabrication, or the like, involved in the stacking of the wiring boards.
However, such a connection pad forms a bottleneck in high-density wiring under recent circumstances where a wiring pitch on board has become small. Specifically, an area occupied by the connection pads is becoming relatively large, resulting in a problem in that the connection pad 9 causes an obstruction to wiring, for example, as shown in FIG. 8, due to being bottlenecked on its size. A part WS indicated by a dashed line in FIG. 8 is a schematic representation of the wiring as not routed due to the size of the connection pad 9. The connection pad is disadvantageous in the high-density wiring, because higher wiring density, in particular, leads to a higher percentage of occupation by the connection pads (specifically, a larger area occupied by the connection pads and also a larger number of connection pads installed).
Also encountered is a problem in that the connection pad does not necessarily provide an electrical interconnection between the boards (or the wiring patterns) therethrough, depending on the degree of misalignment or the like. This is because, although being formed in the appropriate size allowing for the misalignment or the like involved in the stacking, the connection pad has the limit to the “appropriate size” permitted to be designed in view of accuracy such as misalignment under the state of the art.